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mcm63z736 mcm63z818 1 motorola fast sram advance information 128k x 36 and 256k x 18 bit pipelined zbt ? ram synchronous fast static ram the zbt ram is a 4mbit synchronous fast static ram designed to provide zero bus turnaround. the zbt ram allows 100% use of bus cycles during backtoback read/write and write/read cycles. the mcm63z736 is organized as 128k words of 36 bits each and the mcm63z818 is organized as 256k words of 18 bits each, fabricated with high performance silicon gate cmos technology. this device integrates input registers, an output register, a 2bit address counter, and high speed sram onto a single monolithic circuit for reduced parts count in communication applications. synchronous design allows precise cycle control with the use of an external clock (ck). cmos circuitry reduces the overall power consumption of the integrated functions for greater reliability. addresses (sa), data inputs (dq), and all control signals except output enable (g ) and linear burst order (lbo ) are clock (ck) controlled through positive edgetriggered noninverting registers. write cycles are internally selftimed and are initiated by the rising edge of the clock (ck) input. this feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incoming signals. for read cycles, pipelined sram output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock (ck). ? 3.3 v lvttl and lvcmos compatible ? mcm63z736/mcm63z818133 = 4.2 ns access/7.5 ns cycle (133 mhz) mcm63z736/mcm63z818100 = 5 ns access/10 ns cycle (100 mhz) ? selectable burst sequencing order (linear/interleaved) ? internally selftimed write cycle ? twocycle deselect ? byte write control ? adv controlled burst ? 100pin tqfp package zbt and zero bus turnaround are trademarks of integrated device technology, inc., and the architecture is supported by micron technology, inc. and motorola, inc. this document contains information on a new product. specifications and information herein are subject to change without notice. order this document by mcm63z736/d semiconductor technical data mcm63z736 mcm63z818 tq package tqfp case 983a01 rev 1 2/6/98 ? motorola, inc. 1998
mcm63z736 mcm63z818 2 motorola fast sram pin assignment 71 72 dqc v ddq dqb 69 70 66 67 68 64 65 61 62 63 3738 34 35 36 42 43 39 40 41 4546 44 60 59 58 57 56 55 54 53 52 51 31 32 33 74 75 76 77 78 79 80 50 49 48 47 dqb dqb v ss dqb dqb dqb dqb v ss v ddq dqb dqb v ddq v ss v ss v ddq dqc dqc dqc dqc dqc dqc dqc sa sa se1 sbd ck sbc nc g sa0 sa sa sa sa nc nc nc lbo sa1 v dd v dd dqa v ss dqa dqa dqa dqa v ss v ddq dqa dqa v ss v ddq dqa dqa dqd v dd v ss v ss v ddq dqd dqd dqd dqd dqd 73 dqc 94 93 97 9695 89 88 92 91 90 86 85 87 100 99 98 81 82 83 84 10 9 12 11 15 14 13 17 16 20 19 18 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 8 sa sa cke se2 se3 v ss v dd v ddq v ss dqd dqd dqd sa sa sa sa sa sa sa nc v ss nc adv sw sba sbb v dd v dd v ss v dd top view mcm63z736
mcm63z736 mcm63z818 3 motorola fast sram pin assignment 71 72 nc v ddq sa 69 70 66 67 68 64 65 61 62 63 3738 34 35 36 42 43 39 40 41 4546 44 60 59 58 57 56 55 54 53 52 51 31 32 33 74 75 76 77 78 79 80 50 49 48 47 nc nc v ss dqa nc dqa dqa v ss v ddq dqa dqa v ddq v ss v ss v ddq nc nc nc dqb dqb dqb dqb sa sa se1 nc ck nc nc g sa0 sa sa sa sa nc nc nc sa1 v dd v dd dqa v ss dqa dqa nc dqa v ss v ddq nc nc v ss v ddq nc nc dqb v dd v ss v ss v ddq dqb dqb dqb dqb nc 73 nc 94 93 97 9695 89 88 92 91 90 86 85 87 100 99 98 81 82 83 84 10 9 12 11 15 14 13 17 16 20 19 18 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 8 sa sa cke se2 se3 v ss v dd v ddq v ss nc nc nc sa sa sa sa sa sa sa nc v ss nc adv sw sba sbb v dd v dd v ss v dd top view mcm63z818 lbo
mcm63z736 mcm63z818 4 motorola fast sram mcm63z736 pin descriptions pin locations symbol type description 85 adv input synchronous load /advance: loads a new address into counter when low. ram uses internally generated burst addresses when high. 89 ck input clock: this signal registers the address, data in, and all control signals except g and lbo . 87 cke input clock enable: disables the ck input when cke is high. (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b, c, d). 86 g input asynchronous output enable. 31 lbo input linear burst order input: this pin must remain in steady state (this signal not registered or latched). it must be tied high or low. low linear burst counter. high interleaved burst counter. 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 99, 100 sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 36, 37 sa0, sa1 input synchronous burst address inputs: the two lsb's of the address field. these pins must preset the burst address counter values. these inputs are registered and must meet setup and hold times. 93, 94, 95, 96 (a) (b) (c) (d) sbx input synchronous byte write inputs: enables write to byte axo (byte a, b, c, d) in conjunction with sw . has no effect on read cycles. 98 se1 input synchronous chip enable: active low to enable chip. 97 se2 input synchronous chip enable: active high for depth expansion. 92 se3 input synchronous chip enable: active low for depth expansion. 88 sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. 14, 15, 16, 41, 65, 66, 91 v dd supply core power supply. 4, 11, 20, 27, 54, 61, 70, 77 v ddq supply i/o power supply. 5, 10, 17, 21, 26, 40, 55, 60, 64, 67, 71, 76, 90 v ss supply ground. 38, 39, 42, 43, 83, 84 nc e no connection: there is no connection to the chip.
mcm63z736 mcm63z818 5 motorola fast sram mcm63z818 pin descriptions pin locations symbol type description 85 adv input synchronous load /advance: loads a new address into counter when low. ram uses internally generated burst addresses when high. 89 ck input clock: this signal registers the address, data in, and all control signals except g and lbo . 87 cke input clock enable: disables the ck input when cke is high. (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b). 86 g input asynchronous output enable. 31 lbo input linear burst order input: this pin must remain in steady state (this signal not registered or latched). it must be tied high or low. low linear burst counter. high interleaved burst counter. 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 99, 100 sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 36, 37 sa0, sa1 input synchronous burst address inputs: the two lsb's of the address field. these pins must preset the burst address counter values. these inputs are registered and must meet setup and hold times. 93, 94 (a) (b) sbx input synchronous byte write inputs: enables write to byte axo (byte a, b) in conjunction with sw . has no effect on read cycles. 98 se1 input synchronous chip enable: active low to enable chip. 97 se2 input synchronous chip enable: active high for depth expansion. 92 se3 input synchronous chip enable: active low for depth expansion. 88 sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. 14, 15, 16, 41, 65, 66, 91 v dd supply core power supply. 4, 11, 20, 27, 54, 61, 70, 77 v ddq supply i/o power supply. 5, 10, 17, 21, 26, 40, 55, 60, 64, 67, 71, 76, 90 v ss supply ground. 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 75, 78, 79, 83, 84, 95, 96 nc e no connection: there is no connection to the chip.
mcm63z736 mcm63z818 6 motorola fast sram truth table ck cke e sw sbx adv sa0 sax next operation input command code notes lh 1 x x x x x hold h 1, 2 lh 0 false x x 0 x deselect d 1, 2 lh 0 true 0 v 0 v load address, new write w 1, 2, 3, 4, 5 lh 0 true 1 x 0 v load address, new read r 1, 2 lh 0 x x v (w) 1 x burst b 1, 2, 4, 67 x (r, d) continue 6, 7 notes: 1. x = don`t care, 1 = logic high, 0 = logic low, v = valid signal, according to ac operating conditions and characteristics. 2. e = true if se1 and se3 = 0, and se2 = 1. 3. byte write enables, sbx are evaluated only as new write addresses are loaded. 4. no control inputs except cke , sbx , and adv are recognized in a clock cycle where adv is sampled high. 5. a write with sbx not valid does load addresses. 6. a burst write with sbx not valid does increment address. 7. adv controls whether the ram enters burst mode. if the previous cycle was a write, then adv = 1 results in a burst write. if the previous cycle is a read, then adv = 1 results in a burst read. adv = 1 will also continue a deslect cycle. write truth table cycle type sw sba sbb sbc (see note 1) sbd (see note 1) read h x x x x write byte a l l h h h write byte b l h l h h write byte c (see note 1) l h h l h write byte d (see note 1) l h h h l write all bytes l l l l l note: 1. valid only for mcm63z736. linear burst address table (lbo = v ss ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x10 x . . . x11 x . . . x00 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x00 x . . . x01 x . . . x10 interleaved burst address table (lbo = v dd ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x00 x . . . x11 x . . . x10 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x10 x . . . x01 x . . . x00
mcm63z736 mcm63z818 7 motorola fast sram input command code and state name definition diagram false e ck cke true true sa0 sax valid valid sw adv valid valid sbx dbw brbh deselect continue deselect new write burst write new read burst read hold input command code note: cycles are named for their control inputs, not for data i/o state.
mcm63z736 mcm63z818 8 motorola fast sram figure 1. zbt ram state diagram deselect burst write burst read w r d new write new read b w r w r w b b b r b r d d w d d current state (n) next state (n + 1) transition ? input command code key: notes: 1. input command codes (d, w, r, and b) represent control pin inputs as indicated in the truth table. 2. hold (i.e., cke sampled high) is not shown simply because cke = 1 blocks clock input and therefore, blocks any state change. ck command code state ? dq n n + 1 n + 2 n + 3 current state next state figure 2. state definitions for zbt ram state diagram
mcm63z736 mcm63z818 9 motorola fast sram figure 3. data i/o state diagram highz highz (data in) data out (q valid) w r b w current state (n) next state (n + 2) transition ? input command code key: intermediate intermediate intermediate intermediate intermediate b r d d w r intermediate d b notes: 1. input command codes (d, w, r, and b) represent control pin inputs as indicated in the truth table. 2. hold (i.e., cke sampled high) is not shown simply because cke = 1 blocks clock input and therefore, blocks any state change. intermediate state (n + 1) transition ck command code state state name ? dq n n + 1 n + 2 n + 3 current state intermediate state next state figure 4. state definitions for i/o state diagrams
mcm63z736 mcm63z818 10 motorola fast sram absolute maximum ratings (see note 1) rating symbol value unit notes power supply voltage v dd 0.5 to + 4.6 v i/o supply voltage v ddq v ss 0.5 to v dd v 2 input voltage relative to v ss for any pin except v dd v in , v out 0.5 to v dd + 0.5 v 2 input voltage (three state i/o) v it v ss 0.5 to v ddq + 0.5 v 2 output current (per i/o) i out 20 ma package power dissipation p d 1.3 w 3 temperature under bias t bias 10 to 85 c storage temperature t stg 55 to 125 c notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. this is a steadystate dc parameter that is in effect after the power supply has achieved its nominal operating level. power sequencing is not necessary. 3. power dissipation capability is dependent upon package characteristics and use environment. see package thermal characteristics. package thermal characteristics thermal resistance symbol max unit notes junction to ambient (@ 200 lfm) singlelayer board fourlayer board r q ja 40 25 c/w 1, 2 junction to board (bottom) r q jb 17 c/w 3 junction to case (top) r q jc 9 c/w 4 notes: 1. junction temperature is a function of onchip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. per semi g3887. 3. indicates the average thermal resistance between the die and the printed circuit board. 4. indicates the average thermal resistance between the die and the case top surface via the cold plate method (mil spec883 method 1012.1). this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit.
mcm63z736 mcm63z818 11 motorola fast sram dc operating conditions and characteristics (v dd = 3.3 v 5%, t a = 0 to 70 c unless otherwise noted) recommended operating conditions (voltages referenced to v ss = 0 v) parameter symbol min typ max unit supply voltage v dd 3.135 3.3 3.465 v i/o supply voltage v ddq * 3.135 3.3 v dd v input low voltage v il 0.3 e 0.8 v input high voltage v ih 2 e v dd + 0.3 v input high voltage i/o pins v ih2 2 e v ddq + 0.3 v *v dd and v ddq are shorted together on the device and must be supplied with identical voltage levels. v ih 20% t khkh (min) v ss v ss 1.0 v figure 5. undershoot voltage dc characteristics and supply currents parameter symbol min typ max unit notes input leakage current (0 v v in v dd ) i lkg(i) e e 1 m a 1 output leakage current (0 v v in v ddq ) i lkg(o) e e 1 m a ac supply current (device selected, all outputs open, freq = max) includes supply current for both v dd and v ddq i dda e e 350 ma 2, 3, 4 cmos standby supply current (device deselected , freq = 0, v dd = max, v ddq = max, all inputs static at cmos levels) i sb2 e e 5 ma 5, 6 ttl standby supply current (device deselected, freq = 0, v dd = max, v ddq = max, all inputs static at ttl levels) i sb3 e e 25 ma 5, 7 hold supply current (device selected, freq = max, v dd = max, v ddq = max, cke v dd 0.2 v, all inputs static at cmos levels) i dd1 e e 15 ma 6 output low voltage (i ol = 8 ma) v ol e e 0.4 v output high voltage (i oh = 8 ma) v oh 2.4 e e v notes: 1. lbo has an internal pullup and will exhibit leakage currents of 5 m a. 2. reference ac operating conditions and characteristics for input and timing. 3. all addresses transition simultaneously low (lsb) then high (msb). 4. data states are all zero. 5. device in deselected mode as defined by the truth table. 6. cmos levels for i/os are v it v ss + 0.2 v or v ddq 0.2 v. cmos levels for other inputs are v in v ss + 0.2 v or v dd 0.2 v. 7. ttl levels for i/o's are v it v il or v ih2 . ttl levels for other inputs are v in v il or v ih . capacitance (f = 1.0 mhz, dv = 3.0 v, t a = 0 to 70 c, periodically sampled rather than 100% tested) parameter symbol min typ max unit input capacitance c in e 4 5 pf input/output capacitance c i/o e 7 8 pf
mcm63z736 mcm63z818 12 motorola fast sram ac operating conditions and characteristics (v dd = 3.3 v 5%, t a = 0 to 70 c unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 1 v/ns (20% to 80%) . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 6 unless otherwise noted . . . . . . . . . . . . . . r q ja under test tbd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . read/write cycle timing (see notes 1 and 2) p sbl mcm63z736133 mcm63z818133 133 mhz mcm63z736100 mcm63z818100 100 mhz ui n parameter symbol min max min max unit notes cycle time t khkh 7.5 e 10 e ns clock high pulse width t khkl 3 e 4 e ns 3 clock low pulse width t klkh 3 e 4 e ns 3 clock access time t khqv e 4.2 e 5 ns output enable to output valid t glqv e 4.2 e 5 ns clock high to output active t khqx1 1.5 e 1.5 e ns 4, 5 output hold time t khqx 1.5 e 1.5 e ns 4 output enable to output active t glqx 0 e 0 e ns 4, 5 output disable to q highz t ghqz e 3.5 e 3.5 ns 4, 5 clock high to q highz t khqz 1.5 3.5 1.5 3.5 ns 4, 5 setup times: address adv data in write chip enable clock enable t adkh t lvkh t dvkh t wvkh t evkh t cvkh 2 2 1.7 2 2 2 e 2.2 2.2 2 2.2 2.2 2.2 e ns hold times: address adv data in write chip enable clock enable t khax t khlx t khdx t khwx t khex t khcx 0.5 e 0.5 e ns notes: 1. write is defined as any sbx and sw low. chip enable is defined as se1 low, se2 high, and sb3 low whenever adv is low. 2. all read and write cycle timings are referenced from ck or g . 3. in order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, fsram ac parametric specifications are always specified at v ddq /2. in some de- sign exercises, it is desirable to evaluate timing using other reference levels. since the maximum test input edge rate is known and is given in the ac test conditions section of the data sheet as 1 v/ns, one can easily interpolate timing values to other reference levels. 4. this parameter is sampled and not 100% tested. 5. measured at 200 mv from steady state. output z 0 = 50 w r l = 50 w 1.5 v figure 6. ac test load
mcm63z736 mcm63z818 13 motorola fast sram ck sa0 sax figure 7. ac timing parameter definitions t khkh t khkl t klkh t avkh t khax sw t wvkh t khwx sbx t wvkh t khwx e t evkh t khex adv t lvkh t khlx cke t cvkh t khcx g dq q dq dq t khqx1 q t khqz q t khqv t ghqz t glqx t glqv t khqx t dvkh t khdx d
mcm63z736 mcm63z818 14 motorola fast sram read/write cycles with hold and deselect cycles ck command ab c d e fg h ij rw hr w d rh wr dw rd q(a0) d(b0) q(c0) d(d0) q(e0) d(f0) q(g0) d(h0) q(i0) address code dq note: command code definitions are shown in truth table.
mcm63z736 mcm63z818 15 motorola fast sram read cycles (single, burst, and burst wraparound) ck command ab c rr bb b r bb bb address code dq q(a0) q(b0) q(b1) q(b2) q(b3) q(c0) q(c1) q(c2) q(c3) q(c0) note: command code definitions are shown in truth table.
mcm63z736 mcm63z818 16 motorola fast sram write cycles (single, burst, and burst wraparound) ck command ab c ww bb b w bb bb address code dq d(a0) d(b0) d(b1) d(b2) d(b3) d(c0) d(c1) d(c2) d(c3) d(c0) note: command code definitions are shown in truth table.
mcm63z736 mcm63z818 17 motorola fast sram read, write, read coherency with hold, and deselect cycles ck command ab c rw rw b r bd wh address code dq q(a0) d(b0) q(b0) d(c0) d(c1) q(c0) q(c1) d(d0) bc d de rr q(d0) q(e0) note: command code definitions are shown in truth table.
mcm63z736 mcm63z818 18 motorola fast sram mcm 63z818 xx x x motorola memory prefix part number full part numbers e mcm63z736tq133 mcm63z736tq100 mcm63z736tq133r mcm63z736tq100r mcm63z818tq133 mcm63z818tq100 MCM63Z818TQ133R mcm63z818tq100r package (tq = tqfp) blank = trays, r = tape and reel speed (133 = 133 mhz, 100 = 100 mhz) ordering information (order by full part number) 63z736
mcm63z736 mcm63z818 19 motorola fast sram package dimensions tq package 100pin tqfp case 983a01 dim min max min max inches millimeters a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 b1 0.22 0.33 0.009 0.013 c 0.09 0.20 0.004 0.008 c1 0.09 0.16 0.004 0.006 d 22.00 bsc 0.866 bsc e 16.00 bsc 0.630 bsc e1 14.00 bsc 0.551 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 l1 1.00 ref 0.039 ref l2 0.50 ref s 0.20 0.008 r1 0.08 0.003 r2 0.08 0.20 0.003 0.008 0 7 0 7 0 0 11 13 11 13 11 13 11 13 1 2 3 d1 20.00 bsc 0.787 bsc 0.020 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane h. 5. dimensions d and e to be determined at seating plane c. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions d1 and b1 do include mold mismatch and are determined at datum plane h. 7. dimension b does not include dambar protrusion. dambar protrusion shall not cause the b dimension to exceed 0.45 (0.018). ab 0.20 (0.008) h e d ab 0.20 (0.008) c d ab 0.20 (0.008) c d 0.10 (0.004) c 0.25 (0.010) s 0.05 (0.002) s ab m 0.13 (0.005) d s c e/2 d/2 e e1 d1 d d1/2 e1/2 e/2 4x 2x 30 tips 2x 20 tips d b a c h 1 3 2 100 81 80 51 50 31 30 1 plating section bb c1 c b b1 ???? ???? ???? base metal a seating plane view ab s view ab a2 a1 r1 l2 l l1 r2 gage plane x view y b b x=a, b, or d
mcm63z736 mcm63z818 20 motorola fast sram motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed: motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 141, p.o. box 5405, denver, colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 nishi-gotanda, shagawa-ku, tokyo, japan. 03-5487-8488 mfax ? : rmfax0@email.sps.mot.com t ouchtone 1-602-244-6609 asia / pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, motorola fax back system us & c anada only 1-800-774-1848 51 ting kok road, tai po, n.t., hong kong. 852-26629298 http ://sps.motorola.com /mfax / home page : http ://motorola.com/sps / customer focus center: 1-800-521-6274 mcm63z736/d ?

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